Semiconductor industry celebrates 20th Anniversary for Cu Interconnects

Electron Device Society (EDS), IBM, State University of New York (SUNY) and Global Foundries are celebrating the introduction of Cu interconnects to the semiconductor industry at IEEE Nanotechnology Symposium in Albany, NY. We are very proud and pleased to recognize technical leaders for their outstanding contributions towards this milestone.

IEEE conference is hosting Dr. Dan Edelstein, IBM Fellow and one of the pioneers for Cu Interconnects, as our key note speaker. In addition to Dan’s retrospective, we will have a reception with some of the luminaries in the field who enabled first Cu interconnects in 1997. The awards ceremony will be held at the Nanofab South Auditorium, Center for Nanoscale Science and Engineering (CNSE) on Nov 15th from 5 to 5:30 PM.

Please register at the home page to attend the event.

Award Recipients

Daniel Edelstein (IBM Fellow)
C K Hu (IBM)
Paul McLaughlin (IBM)
Rick Wachnik (IBM)
Lili Deligianni (IBM)
Emmanuel Crabbe (IBM)
Andy Simon (GF)
Tom McDevitt (GF)
Tony Stamper (GF)
Glenn Biery (GF)
Bill Cote (Retired)
Naftali Lustig (IBM)
Steve Luce (GF)

Guests of Honor

John Kelly III (Senior Vice President, Cognitive Solutions and IBM Research, IBM)
Mukesh Khare (Vice President, Semiconductor Technology Research, IBM)
Bahgat G. Sammakia (Interim President, SUNY)
T.C. Chen (Vice President Science & Technology, IBM Fellow, IBM)
Bijan Davari (Vice President, Next Generation Computing Systems and Technology, IBM Fellow, IBM)
George Gomba (Vice President, Technology Research, GLOBALFOUNDRIES)
Thomas N. Theis (Executive Director, Columbia Nano Initiative, Columbia University)
Kang-ill Seo (Vice President, R & D, Samsung Semiconductor Inc.)

1997 IBM BEOL team that enabled first commerical Cu interconnects

 

MRS Bulletin 1995 Cu pennies cover photo

Copper Interconnects in Chip

In 1997 up to six levels of copper interconnects on a chip were possible. Modern copper interconnects are 10 times smaller, allowing up to 13 to 15 levels of interconnects to be laid out on chip